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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
| commit | 020606f81c39df234d7a3f5e3e605e5f27422d87 (patch) | |
| tree | 8334168ea6ad76983226fa3bbc631ff151d4fedd /tests/arch/xilinx/tribuf.ys | |
| parent | 36d79c80d05f93cd4cb565fe7a92d7cb88683852 (diff) | |
| parent | b5f60e055d07579a2d4f23fc053ca030f103f377 (diff) | |
| download | yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.gz yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.bz2 yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.zip | |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
Diffstat (limited to 'tests/arch/xilinx/tribuf.ys')
| -rw-r--r-- | tests/arch/xilinx/tribuf.ys | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index 4697703ca..eaccab126 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -7,6 +7,7 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D +select -assert-count 2 t:IBUF +select -assert-count 1 t:INV +select -assert-count 1 t:OBUFT +select -assert-none t:IBUF t:INV t:OBUFT %% t:* %D |