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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-12-30 20:34:31 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-30 20:34:31 +0100 |
| commit | c0a17c2457532726b05586d3b7a030bd9f372dea (patch) | |
| tree | 7db5e128665cb486880bcf7c01e08cc060a3469d /tests/arch/xilinx/mux.ys | |
| parent | c2c74f9bb001bba026270a6c218fc462aeaac6c2 (diff) | |
| parent | f9749c202c93e1c9c6edb522999eacc323039b95 (diff) | |
| download | yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.gz yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.bz2 yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.zip | |
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Diffstat (limited to 'tests/arch/xilinx/mux.ys')
| -rw-r--r-- | tests/arch/xilinx/mux.ys | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 388272449..99817738d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -14,7 +14,7 @@ select -assert-none t:LUT3 %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT6 @@ -25,7 +25,7 @@ select -assert-none t:LUT6 %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -37,7 +37,7 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-min 5 t:LUT6 |