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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-12-30 20:34:31 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-30 20:34:31 +0100 |
| commit | c0a17c2457532726b05586d3b7a030bd9f372dea (patch) | |
| tree | 7db5e128665cb486880bcf7c01e08cc060a3469d /tests/arch/xilinx/lutram.ys | |
| parent | c2c74f9bb001bba026270a6c218fc462aeaac6c2 (diff) | |
| parent | f9749c202c93e1c9c6edb522999eacc323039b95 (diff) | |
| download | yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.gz yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.bz2 yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.zip | |
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Diffstat (limited to 'tests/arch/xilinx/lutram.ys')
| -rw-r--r-- | tests/arch/xilinx/lutram.ys | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 6c9d1eae1..3f127a77e 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -2,7 +2,7 @@ #hierarchy -top lutram_1w1r -chparam A_WIDTH 4 #proc #memory -nomap -#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad #memory #opt -full # @@ -22,7 +22,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -42,7 +42,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -62,7 +62,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -82,7 +82,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r -chparam A_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -102,7 +102,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -122,7 +122,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full |