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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:22:24 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:22:24 +0100 |
| commit | a82c701668d8197c01e54cb68bc45f2278f3172f (patch) | |
| tree | cf7a692d2a470c5e045caa9a9bb8a0a6e8886880 /tests/arch/xilinx/counter.ys | |
| parent | 509da7ed1a1e27066451f57868108b473cf516a0 (diff) | |
| download | yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.tar.gz yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.tar.bz2 yosys-a82c701668d8197c01e54cb68bc45f2278f3172f.zip | |
Make test without iopads
Diffstat (limited to 'tests/arch/xilinx/counter.ys')
| -rw-r--r-- | tests/arch/xilinx/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 604acdbfc..11c29922e 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |