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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
| commit | 53a99ade9cbab883de5d1dcc30ad89d75266df7f (patch) | |
| tree | 17808f6ffdfdd90c44a56aaddf626d5884a821a3 /tests/arch/xilinx/counter.ys | |
| parent | 531fddf797a79b46df3e462112ca68ff50e6a18e (diff) | |
| parent | 61ffd2d1996befd8c27c4f36f07567824bd7605e (diff) | |
| download | yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.gz yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.bz2 yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'tests/arch/xilinx/counter.ys')
| -rw-r--r-- | tests/arch/xilinx/counter.ys | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 11c29922e..064519ce7 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -5,10 +5,9 @@ flatten equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 8 t:FDCE select -assert-count 1 t:INV -select -assert-count 7 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D +select -assert-count 2 t:CARRY4 +select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D |