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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-12-30 20:34:31 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-30 20:34:31 +0100 |
| commit | c0a17c2457532726b05586d3b7a030bd9f372dea (patch) | |
| tree | 7db5e128665cb486880bcf7c01e08cc060a3469d /tests/arch/xilinx/add_sub.ys | |
| parent | c2c74f9bb001bba026270a6c218fc462aeaac6c2 (diff) | |
| parent | f9749c202c93e1c9c6edb522999eacc323039b95 (diff) | |
| download | yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.gz yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.tar.bz2 yosys-c0a17c2457532726b05586d3b7a030bd9f372dea.zip | |
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Diffstat (limited to 'tests/arch/xilinx/add_sub.ys')
| -rw-r--r-- | tests/arch/xilinx/add_sub.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..313948cc5 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 |