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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 12:22:39 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
commit | 7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10 (patch) | |
tree | 103caee23d30a3a81fe1a56cd88dd5523df486c2 /tests/arch/xilinx/abc9_dff.ys | |
parent | bb840cca9cd62ad59b2054049e979263325ba664 (diff) | |
download | yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.tar.gz yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.tar.bz2 yosys-7cd3f4a79bde6dbe2cd7f90d0a4996aebe70fd10.zip |
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
Diffstat (limited to 'tests/arch/xilinx/abc9_dff.ys')
-rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index 15343970f..fd343969b 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -46,16 +46,40 @@ FDCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); FDPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4])); FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5])); -FDCE_1 #(.INIT(1)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); +FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7])); endmodule EOT -logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$_DFF_P_ cell .*" 1 -logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 -logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1 -logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 +logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1 +logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1 +logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1 +logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt select -assert-count 8 t:FD* + +design -reset +read_verilog <<EOT +module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1); +always @(posedge clk or posedge clr) + if (clr) + q0 <= 1'b0; + else + q0 <= ~q0; +always @(posedge clk or posedge pre) + if (pre) + q1 <= 1'b1; + else + q1 <= ~q1; +endmodule +EOT +proc +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-count 1 t:FDCE +select -assert-count 1 t:FDPE +select -assert-count 2 t:INV +select -assert-count 0 t:FD* t:INV %% t:* %D + logger -expect-no-warnings |