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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-04-20 18:52:36 +0200 |
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| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-04-20 18:52:36 +0200 |
| commit | 46d3f03d27b4851b64f909ddbb663cbdac0fed70 (patch) | |
| tree | 191f8ae8212a68942e5d31d62c4135deb4d38df2 /tests/arch/quicklogic | |
| parent | 8aee80040de0b0812f2aec7ba4059c14407a0567 (diff) | |
| download | yosys-46d3f03d27b4851b64f909ddbb663cbdac0fed70.tar.gz yosys-46d3f03d27b4851b64f909ddbb663cbdac0fed70.tar.bz2 yosys-46d3f03d27b4851b64f909ddbb663cbdac0fed70.zip | |
Add default assignments to other SB_* simulation models
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'tests/arch/quicklogic')
0 files changed, 0 insertions, 0 deletions