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author | Lofty <dan.ravensloft@gmail.com> | 2021-03-17 02:34:30 +0000 |
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committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-18 13:28:16 +0100 |
commit | f4298b057ae0939b83283c8c7431097e71a32b62 (patch) | |
tree | eedd3de21b55af0c2952fd8e730fb165c89fa8a3 /tests/arch/quicklogic/tribuf.ys | |
parent | 8740fdf1d799fd8a3196bac28fe4e418e74f2acc (diff) | |
download | yosys-f4298b057ae0939b83283c8c7431097e71a32b62.tar.gz yosys-f4298b057ae0939b83283c8c7431097e71a32b62.tar.bz2 yosys-f4298b057ae0939b83283c8c7431097e71a32b62.zip |
quicklogic: PolarPro 3 support
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
Diffstat (limited to 'tests/arch/quicklogic/tribuf.ys')
-rw-r--r-- | tests/arch/quicklogic/tribuf.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys new file mode 100644 index 000000000..de763009e --- /dev/null +++ b/tests/arch/quicklogic/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 2 t:inpad +select -assert-count 1 t:outpad +select -assert-count 1 t:$_TBUF_ +select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D |