diff options
| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-11-19 10:19:00 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-15 11:40:41 +0200 |
| commit | 2e37e62e6b926ca1712b1636ef720748e382dc97 (patch) | |
| tree | 25936d690dff24f0cddcc5dbbfe68aea74500994 /tests/arch/intel_alm/tribuf.ys | |
| parent | 4c52691a58a469a525401bbc83c65f262b2a5504 (diff) | |
| download | yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.gz yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.tar.bz2 yosys-2e37e62e6b926ca1712b1636ef720748e382dc97.zip | |
synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
Diffstat (limited to 'tests/arch/intel_alm/tribuf.ys')
| -rw-r--r-- | tests/arch/intel_alm/tribuf.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys new file mode 100644 index 000000000..71b05a747 --- /dev/null +++ b/tests/arch/intel_alm/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ + +select -assert-none t:$_TBUF_ %% t:* %D |