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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-05 18:53:14 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 21:36:38 +0200 |
| commit | 0d4c2f0a65de2fccd767a56b9698be3d913fdd9f (patch) | |
| tree | 1a893fd344cc7be071d175c9183bb9d10ffa89a5 /tests/arch/intel_alm/tribuf.ys | |
| parent | b5f3b70cfeed9421e6d0daa3a1ef968b2b670bc2 (diff) | |
| download | yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.gz yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.tar.bz2 yosys-0d4c2f0a65de2fccd767a56b9698be3d913fdd9f.zip | |
intel_alm: add Cyclone 10 GX tests
Diffstat (limited to 'tests/arch/intel_alm/tribuf.ys')
| -rw-r--r-- | tests/arch/intel_alm/tribuf.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys index 71b05a747..7f3b38493 100644 --- a/tests/arch/intel_alm/tribuf.ys +++ b/tests/arch/intel_alm/tribuf.ys @@ -9,5 +9,19 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D + +design -reset +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D |