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| author | gatecat <gatecat@ds0.me> | 2021-05-15 14:23:22 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 22:37:06 +0100 |
| commit | 5dba138c87762d4b5bb7b9348da372a92fab1cc0 (patch) | |
| tree | 764f5d928b3e06b6a4884d5d1b14e4533003d18e /tests/arch/intel_alm/mul.ys | |
| parent | 3421979f00664443c77b0899d34438f979b4c51c (diff) | |
| download | yosys-5dba138c87762d4b5bb7b9348da372a92fab1cc0.tar.gz yosys-5dba138c87762d4b5bb7b9348da372a92fab1cc0.tar.bz2 yosys-5dba138c87762d4b5bb7b9348da372a92fab1cc0.zip | |
intel_alm: Add IO buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'tests/arch/intel_alm/mul.ys')
| -rw-r--r-- | tests/arch/intel_alm/mul.ys | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys index 49934740f..10f3f7bf4 100644 --- a/tests/arch/intel_alm/mul.ys +++ b/tests/arch/intel_alm/mul.ys @@ -2,7 +2,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -16,7 +16,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -28,7 +28,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -40,7 +40,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -52,7 +52,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |