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authorgatecat <gatecat@ds0.me>2021-05-15 14:40:37 +0100
committergatecat <gatecat@ds0.me>2021-05-15 22:37:06 +0100
commit34a08750fa1a490be09411b07f64f4236eff234e (patch)
tree5fbb25ea584e2183d57d4a2de46d23cdd1438497 /tests/arch/intel_alm/counter.ys
parenteb106732d94322fb5b48fbff0420ce5a6fc83eb9 (diff)
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intel_alm: Fix illegal carry chains
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'tests/arch/intel_alm/counter.ys')
-rw-r--r--tests/arch/intel_alm/counter.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index f2f3f14f7..56c9cabb3 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -6,7 +6,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
@@ -21,7 +21,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
select -assert-count 8 t:MISTRAL_ALUT_ARITH
select -assert-count 8 t:MISTRAL_FF
select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D