diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
| commit | 136842b1ef18b850b518705ff3e6df3958f28e0c (patch) | |
| tree | abcdddaf53bafd5e34e9aa278ffbe3d001b60cc4 /tests/arch/ice40/bug1598.ys | |
| parent | 705e520a527864dc32f1934bb4b2b94d75f8f0ec (diff) | |
| parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
| download | yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.gz yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.bz2 yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.zip | |
Merge branch 'master' into eddie/submod_po
Diffstat (limited to 'tests/arch/ice40/bug1598.ys')
| -rw-r--r-- | tests/arch/ice40/bug1598.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys new file mode 100644 index 000000000..8438cb979 --- /dev/null +++ b/tests/arch/ice40/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 |