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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:44:00 -0800 |
commit | 020606f81c39df234d7a3f5e3e605e5f27422d87 (patch) | |
tree | 8334168ea6ad76983226fa3bbc631ff151d4fedd /tests/arch/ice40/bug1598.ys | |
parent | 36d79c80d05f93cd4cb565fe7a92d7cb88683852 (diff) | |
parent | b5f60e055d07579a2d4f23fc053ca030f103f377 (diff) | |
download | yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.gz yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.tar.bz2 yosys-020606f81c39df234d7a3f5e3e605e5f27422d87.zip |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
Diffstat (limited to 'tests/arch/ice40/bug1598.ys')
-rw-r--r-- | tests/arch/ice40/bug1598.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys new file mode 100644 index 000000000..8438cb979 --- /dev/null +++ b/tests/arch/ice40/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 |