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| author | gatecat <gatecat@ds0.me> | 2022-11-10 09:53:07 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2022-11-17 13:34:58 +0100 |
| commit | f111bbdf4006be9f108374c8591c682f02033a6f (patch) | |
| tree | b58516ae81544d77c51748dc6c8bed84bf23bce1 /tests/arch/fabulous/logic.ys | |
| parent | e3f9ff267929001965348e200d5e6edbfd2d0039 (diff) | |
| download | yosys-f111bbdf4006be9f108374c8591c682f02033a6f.tar.gz yosys-f111bbdf4006be9f108374c8591c682f02033a6f.tar.bz2 yosys-f111bbdf4006be9f108374c8591c682f02033a6f.zip | |
fabulous: improvements to the pass
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'tests/arch/fabulous/logic.ys')
| -rw-r--r-- | tests/arch/fabulous/logic.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/fabulous/logic.ys b/tests/arch/fabulous/logic.ys new file mode 100644 index 000000000..730d9ab54 --- /dev/null +++ b/tests/arch/fabulous/logic.ys @@ -0,0 +1,10 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-max 1 t:LUT1 +select -assert-max 6 t:LUT2 +select -assert-max 2 t:LUT4 +select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D |