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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-11-11 15:41:33 +0100 |
| commit | 3e0ffe05a79d3196b3644cddf422edb927673b04 (patch) | |
| tree | b518fa47c9a27aa37da0deceb66313d769e14c7c /tests/arch/efinix/fsm.ys | |
| parent | 362f4f996d49cca4be240d5c96fba013dd56a8cb (diff) | |
| download | yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.gz yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.tar.bz2 yosys-3e0ffe05a79d3196b3644cddf422edb927673b04.zip | |
Fixed tests
Diffstat (limited to 'tests/arch/efinix/fsm.ys')
| -rw-r--r-- | tests/arch/efinix/fsm.ys | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index a8ba70fdb..a2db2ad98 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -2,9 +2,11 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check + +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module |