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authorEddie Hung <eddie@fpgeh.com>2020-01-06 09:44:00 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-06 09:44:00 -0800
commit020606f81c39df234d7a3f5e3e605e5f27422d87 (patch)
tree8334168ea6ad76983226fa3bbc631ff151d4fedd /tests/arch/ecp5/mul.ys
parent36d79c80d05f93cd4cb565fe7a92d7cb88683852 (diff)
parentb5f60e055d07579a2d4f23fc053ca030f103f377 (diff)
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Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
Diffstat (limited to 'tests/arch/ecp5/mul.ys')
-rw-r--r--tests/arch/ecp5/mul.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys
index 2105be52c..f887e9585 100644
--- a/tests/arch/ecp5/mul.ys
+++ b/tests/arch/ecp5/mul.ys
@@ -3,9 +3,9 @@ hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models)
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+synth_ecp5
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT18X18D
select -assert-none t:MULT18X18D %% t:* %D