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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 14:14:45 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 14:52:38 +0200 |
| commit | b98376884e559330a0de191fadb098eadfe3fe0c (patch) | |
| tree | 2949a12f05e2500f4a1cdd17bcef15727f0e2421 /tests/arch/common | |
| parent | 72d86c327e203a097f15e502e6a90f1e6d345d7e (diff) | |
| download | yosys-b98376884e559330a0de191fadb098eadfe3fe0c.tar.gz yosys-b98376884e559330a0de191fadb098eadfe3fe0c.tar.bz2 yosys-b98376884e559330a0de191fadb098eadfe3fe0c.zip | |
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.
These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations. Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded. Fix it with -deref and manual hierarchy call.
Shaves 30s off the test time on my machine.
Diffstat (limited to 'tests/arch/common')
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