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authorEddie Hung <eddie@fpgeh.com>2020-01-28 12:46:18 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-28 12:46:18 -0800
commita855f23f22c9e6dbba5ff17a9541a7d26342b56a (patch)
treef62715ee5a790615d8d4fcda7814a940608c7310 /tests/arch/common/lutram.v
parentf5e0a07ad679696b0d3077ef877941d4c1f864d7 (diff)
parent7939727d14f44b5d56ca3806d0907e9fceea2882 (diff)
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Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
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diff --git a/tests/arch/common/lutram.v b/tests/arch/common/lutram.v
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+module lutram_1w1r
+#(parameter D_WIDTH=8, A_WIDTH=6)
+(
+ input [D_WIDTH-1:0] data_a,
+ input [A_WIDTH:1] addr_a,
+ input we_a, clk,
+ output reg [D_WIDTH-1:0] q_a
+);
+ // Declare the RAM variable
+ reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ ram[addr_a] <= data_a;
+ q_a <= ram[addr_a];
+ end
+endmodule
+
+
+module lutram_1w3r
+#(parameter D_WIDTH=8, A_WIDTH=5)
+(
+ input [D_WIDTH-1:0] data_a, data_b, data_c,
+ input [A_WIDTH:1] addr_a, addr_b, addr_c,
+ input we_a, clk,
+ output reg [D_WIDTH-1:0] q_a, q_b, q_c
+);
+ // Declare the RAM variable
+ reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ ram[addr_a] <= data_a;
+ q_a <= ram[addr_a];
+ q_b <= ram[addr_b];
+ q_c <= ram[addr_c];
+ end
+endmodule