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author | whitequark <whitequark@whitequark.org> | 2020-04-10 14:51:01 +0000 |
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committer | GitHub <noreply@github.com> | 2020-04-10 14:51:01 +0000 |
commit | 93ef516d919b40ace2099bc7586bfda8648f0757 (patch) | |
tree | ab7e043e1c9d5cd1e6ff5258fd1e6709081200a0 /tests/arch/common/blockrom.v | |
parent | 93c6c6779861d7b41fae1b87d54790e0a9555b80 (diff) | |
parent | 763401fc827d444bfef5a10ff658a3bf7e89b76c (diff) | |
download | yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.gz yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.bz2 yosys-93ef516d919b40ace2099bc7586bfda8648f0757.zip |
Merge pull request #1603 from whitequark/ice40-ram_style
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
Diffstat (limited to 'tests/arch/common/blockrom.v')
-rw-r--r-- | tests/arch/common/blockrom.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/arch/common/blockrom.v b/tests/arch/common/blockrom.v new file mode 100644 index 000000000..93f5c9ddf --- /dev/null +++ b/tests/arch/common/blockrom.v @@ -0,0 +1,31 @@ +`default_nettype none +module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + integer i,j = 64'hF4B1CA8127865242; + initial + for (i = 0; i <= DEPTH; i++) begin + // In case this ROM will be implemented in fabric: fill the memory with some data + // uncorrelated with the address, or Yosys might see through the ruse and e.g. not + // emit any LUTs at all for `memory[i] = i;`, just a latch. + memory[i] = j * 64'h2545F4914F6CDD1D; + j = j ^ (j >> 12); + j = j ^ (j << 25); + j = j ^ (j >> 27); + end + + always @(posedge clk) begin + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; + +endmodule // sync_rom |