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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-25 10:10:21 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:16 +1300 |
| commit | 51c2d476c2209b3dad9e0a0199648274b5c3ea82 (patch) | |
| tree | b7c42bf3837a8ad4091b48ef4140f6e1fd65458e /tests/arch/common/blockram.v | |
| parent | 8f6a06951c7a3da0b5427950f19c0bf5fe67f854 (diff) | |
| download | yosys-51c2d476c2209b3dad9e0a0199648274b5c3ea82.tar.gz yosys-51c2d476c2209b3dad9e0a0199648274b5c3ea82.tar.bz2 yosys-51c2d476c2209b3dad9e0a0199648274b5c3ea82.zip | |
Removing extra `default_nettype` lines
Diffstat (limited to 'tests/arch/common/blockram.v')
| -rw-r--r-- | tests/arch/common/blockram.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 6b557fdca..c06ac96d5 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -22,7 +22,6 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sp -`default_nettype none module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk, write_enable, input wire [DATA_WIDTH-1:0] data_in, @@ -46,7 +45,6 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp -`default_nettype none module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, |