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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 11:25:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 11:25:17 -0700 |
| commit | 317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca (patch) | |
| tree | fecf316c024b8694886b99bcc208c7c4d4d15b72 /tests/arch/anlogic | |
| parent | af16ca9dd4abdbb7c6a2f54f15abb493a4584ce6 (diff) | |
| download | yosys-317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca.tar.gz yosys-317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca.tar.bz2 yosys-317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca.zip | |
Simplify breaking tests/arch/*/fsm.ys tests
Diffstat (limited to 'tests/arch/anlogic')
| -rw-r--r-- | tests/arch/anlogic/fsm.ys | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index 0bcc4e011..eb94177ad 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT2 -select -assert-count 5 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D +select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D |