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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 12:12:02 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 12:12:02 +0300 |
| commit | 27377c46634263beb5f8c28cb34b0c87ed6e9525 (patch) | |
| tree | 45891fbd7f4486d0f90486cca0e42a74b84d8da1 /tests/anlogic/fsm.v | |
| parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
| download | yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.tar.gz yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.tar.bz2 yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.zip | |
Add new tests for Anlogic architecture
Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_ is present.
Diffstat (limited to 'tests/anlogic/fsm.v')
| -rw-r--r-- | tests/anlogic/fsm.v | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/anlogic/fsm.v @@ -0,0 +1,73 @@ + module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3 ;
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+ .reset(rst),
+ .req_0(a),
+ .req_1(b),
+ .gnt_0(g0),
+ .gnt_1(g1));
+
+endmodule
|