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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:04 +0200 |
| commit | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (patch) | |
| tree | a78b5d92952ea9f95623bb3daf8028d2402d023b /tests/anlogic/add_sub.ys | |
| parent | 5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff) | |
| parent | 66fca65b58bfb944cad45da5836613726498e4b7 (diff) | |
| download | yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.gz yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.tar.bz2 yosys-ab4899a2d02b994d79e4aa223eb743793b9a60b3.zip | |
Merge pull request #1434 from YosysHQ/mmicko/anlogic
Add tests for Anlogic architecture (contd)
Diffstat (limited to 'tests/anlogic/add_sub.ys')
| -rw-r--r-- | tests/anlogic/add_sub.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys new file mode 100644 index 000000000..b8b67cc46 --- /dev/null +++ b/tests/anlogic/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 + +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D |