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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 12:12:02 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-23 12:12:02 +0300 |
| commit | 27377c46634263beb5f8c28cb34b0c87ed6e9525 (patch) | |
| tree | 45891fbd7f4486d0f90486cca0e42a74b84d8da1 /tests/anlogic/add_sub.ys | |
| parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
| download | yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.tar.gz yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.tar.bz2 yosys-27377c46634263beb5f8c28cb34b0c87ed6e9525.zip | |
Add new tests for Anlogic architecture
Problems/questions:
- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
- Internal cell type $_TBUF_ is present.
Diffstat (limited to 'tests/anlogic/add_sub.ys')
| -rw-r--r-- | tests/anlogic/add_sub.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys new file mode 100644 index 000000000..55c090506 --- /dev/null +++ b/tests/anlogic/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D + |