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authorEddie Hung <eddie@fpgeh.com>2020-05-02 09:56:10 -0700
committerEddie Hung <eddie@fpgeh.com>2020-05-02 10:00:32 -0700
commit2e78daf1ca68068ca9fa02eca1cc10e64d92cb11 (patch)
tree84c33858ecc9793b55fe8a88947e077edbd23695 /tests/aiger/neg.ys
parenta0afa1787e71fca1fb143a96580136f4bf355251 (diff)
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tests: aiger test for wire->start_offset != 0
Diffstat (limited to 'tests/aiger/neg.ys')
-rw-r--r--tests/aiger/neg.ys36
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/aiger/neg.ys b/tests/aiger/neg.ys
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+read_verilog <<EOT
+module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
+assign c = a & b;
+endmodule
+EOT
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+design -save read
+
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_aiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+
+
+design -load read
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_xaiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i