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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:28:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:28:50 -0700 |
| commit | cf020befeb99df2296f2efe722410e49becb44dd (patch) | |
| tree | 228847b0e33a9b93f6a90665eb1c434139defdb6 /techlibs/xilinx | |
| parent | 0d347e17089eb4b23ef444a7c9adf8420aa2c93e (diff) | |
| download | yosys-cf020befeb99df2296f2efe722410e49becb44dd.tar.gz yosys-cf020befeb99df2296f2efe722410e49becb44dd.tar.bz2 yosys-cf020befeb99df2296f2efe722410e49becb44dd.zip | |
Fix CARRY4 abc_box_id
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 94bc3ef86..3937d3536 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *) +(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; |