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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:33:54 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 10:33:54 -0700 |
commit | 612083a807f0776f13db132ddbd5cf0bed14eb02 (patch) | |
tree | 3b9613b57c2e32f90baaee774e9d9231369ac20f /techlibs/xilinx | |
parent | 177c26ca359f85d0804c62f73e1df1665ffd1ec5 (diff) | |
parent | 988e6163abae4ed0a01952c221d17f70bed9c244 (diff) | |
download | yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.tar.gz yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.tar.bz2 yosys-612083a807f0776f13db132ddbd5cf0bed14eb02.zip |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r-- | techlibs/xilinx/abc_xc7_nowide.lut | 10 | ||||
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 46 |
2 files changed, 45 insertions, 11 deletions
diff --git a/techlibs/xilinx/abc_xc7_nowide.lut b/techlibs/xilinx/abc_xc7_nowide.lut new file mode 100644 index 000000000..fab48c879 --- /dev/null +++ b/techlibs/xilinx/abc_xc7_nowide.lut @@ -0,0 +1,10 @@ +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf +# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json + +# K area delay +1 1 127 +2 2 127 238 +3 3 127 238 407 +4 3 127 238 407 472 +5 3 127 238 407 472 631 +6 5 127 238 407 472 631 642 diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4367f2b99..2a641e933 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -73,6 +73,12 @@ struct SynthXilinxPass : public ScriptPass log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); + log(" -nocarry\n"); + log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n"); + log("\n"); log(" -widemux <int>\n"); log(" enable inference of hard multiplexer resources (MuxFx) for muxes at or\n"); log(" above this number of inputs (minimum value 5).\n"); @@ -99,7 +105,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, abc, arch; - bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl; + bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -107,7 +113,7 @@ struct SynthXilinxPass : public ScriptPass top_opt = "-auto-top"; edif_file.clear(); blif_file.clear(); - abc = "abc"; + arch = "xc7"; flatten = false; retime = false; vpr = false; @@ -115,7 +121,9 @@ struct SynthXilinxPass : public ScriptPass nobram = false; nodram = false; nosrl = false; - arch = "xc7"; + nocarry = false; + nowidelut = false; + abc9 = false; widemux = 0; } @@ -159,6 +167,14 @@ struct SynthXilinxPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } + if (args[argidx] == "-nowidelut") { + nowidelut = true; + continue; + } if (args[argidx] == "-vpr") { vpr = true; continue; @@ -184,7 +200,7 @@ struct SynthXilinxPass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc = "abc9"; + abc9 = true; continue; } break; @@ -321,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass techmap_args += " -map +/xilinx/arith_map.v"; if (vpr) techmap_args += " -D _EXPLICIT_CARRY"; - else if (abc == "abc9") + else if (abc9) techmap_args += " -D _CLB_CARRY"; } run("techmap " + techmap_args); @@ -338,12 +354,20 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { run("opt_expr -mux_undef"); - if (abc == "abc9") - run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : "")); - else if (help_mode) - run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); - else - run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + if (help_mode) + run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')"); + else if (abc9) { + if (nowidelut) + run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + else + run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : "")); + } + else { + if (nowidelut) + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); + else + run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + } run("clean"); // This shregmap call infers fixed length shift registers after abc |