diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-08-22 20:26:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-22 20:31:04 +0200 |
| commit | 5059b3166098044a87b3d0b7f3ae2957df7e6194 (patch) | |
| tree | 56354acd86f6a874e9054774587907ee8e7f3754 /techlibs/xilinx7/counter.v | |
| parent | 39ee561169ba04374c2c630a5ef5a61537a67c13 (diff) | |
| download | yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.tar.gz yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.tar.bz2 yosys-5059b3166098044a87b3d0b7f3ae2957df7e6194.zip | |
Added simple xilinx7 technology mapping files
Diffstat (limited to 'techlibs/xilinx7/counter.v')
| -rw-r--r-- | techlibs/xilinx7/counter.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/xilinx7/counter.v b/techlibs/xilinx7/counter.v new file mode 100644 index 000000000..72208bd80 --- /dev/null +++ b/techlibs/xilinx7/counter.v @@ -0,0 +1,12 @@ +module counter (clk, rst, en, count); + + input clk, rst, en; + output reg [3:0] count; + + always @(posedge clk) + if (rst) + count <= 4'd0; + else if (en) + count <= count + 4'd1; + +endmodule |