Update dff2dffe, dff2dffs, zinit to new FF types.

1 files changed, 12 insertions, 12 deletions

diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
index 2bd874457..750e8f8eb 100644
--- a/techlibs/xilinx/xc7_ff_map.v
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -89,23 +89,23 @@ endmodule
 
 // Async reset, enable.
 
-module  \$__DFFE_NP0 (input D, C, E, R, output Q);
+module  \$_DFFE_NP0P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFE_PP0 (input D, C, E, R, output Q);
+module  \$_DFFE_PP0P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
-module  \$__DFFE_NP1 (input D, C, E, R, output Q);
+module  \$_DFFE_NP1P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFE_PP1 (input D, C, E, R, output Q);
+module  \$_DFFE_PP1P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -113,23 +113,23 @@ endmodule
 
 // Sync reset.
 
-module  \$__DFFS_NP0_ (input D, C, R, output Q);
+module  \$_SDFF_NP0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFS_PP0_ (input D, C, R, output Q);
+module  \$_SDFF_PP0_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
-module  \$__DFFS_NP1_ (input D, C, R, output Q);
+module  \$_SDFF_NP1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFS_PP1_ (input D, C, R, output Q);
+module  \$_SDFF_PP1_ (input D, C, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -137,23 +137,23 @@ endmodule
 
 // Sync reset, enable.
 
-module  \$__DFFSE_NP0 (input D, C, E, R, output Q);
+module  \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFSE_PP0 (input D, C, E, R, output Q);
+module  \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
-module  \$__DFFSE_NP1 (input D, C, E, R, output Q);
+module  \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
-module  \$__DFFSE_PP1 (input D, C, E, R, output Q);
+module  \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
   parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
   FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
   wire _TECHMAP_REMOVEINIT_Q_ = 1;