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| author | David Shah <dave@ds0.me> | 2019-08-08 11:18:37 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:18:37 +0100 |
| commit | d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5 (patch) | |
| tree | de262053843adbc7b4c3b520609eccc2b385e762 /techlibs/xilinx/tests/test_dsp_model.sh | |
| parent | e7dbe7bb3de256f0ea89eb07647799b1e8d65bbe (diff) | |
| download | yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.tar.gz yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.tar.bz2 yosys-d60b3c0dc8ca9ce1b14c4acf2b602acc1fac00c5.zip | |
DSP48E1 sim model: fix seq tests and add preadder tests
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/xilinx/tests/test_dsp_model.sh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/tests/test_dsp_model.sh b/techlibs/xilinx/tests/test_dsp_model.sh index 3c7cfac30..337530e87 100644 --- a/techlibs/xilinx/tests/test_dsp_model.sh +++ b/techlibs/xilinx/tests/test_dsp_model.sh @@ -4,7 +4,8 @@ sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > if [ ! -f "test_dsp_model_ref.v" ]; then cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v fi -for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc +for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \ + mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc do iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v vvp -N ./test_dsp_model |