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| author | luke whittlesey <luke.whittlesey@gmail.com> | 2015-05-10 11:33:24 -0400 |
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| committer | luke whittlesey <luke.whittlesey@gmail.com> | 2015-05-10 11:33:24 -0400 |
| commit | 6de8fea2c77abb936ba2356bf5c1425a15f5edd7 (patch) | |
| tree | ca6e06d250560e918f669c7d566115ba0a5c31d9 /techlibs/xilinx/tests/bram2.v | |
| parent | 2c1e15029786fe8a118343b7a81f681450a8ce93 (diff) | |
| download | yosys-6de8fea2c77abb936ba2356bf5c1425a15f5edd7.tar.gz yosys-6de8fea2c77abb936ba2356bf5c1425a15f5edd7.tar.bz2 yosys-6de8fea2c77abb936ba2356bf5c1425a15f5edd7.zip | |
Made changes recommended by Clifford Wolf ...
Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
Diffstat (limited to 'techlibs/xilinx/tests/bram2.v')
0 files changed, 0 insertions, 0 deletions