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| author | Clifford Wolf <clifford@clifford.at> | 2016-03-19 11:09:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-19 11:09:10 +0100 |
| commit | ff5c61b1207304e97714d40d37c1627510cc08a8 (patch) | |
| tree | 2757c9609c5e8fc306c70a3017949001fe2e274e /techlibs/xilinx/synth_xilinx.cc | |
| parent | ef4207d5ade8254c9b0f63cac2ad5fee310362d4 (diff) | |
| download | yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.tar.gz yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.tar.bz2 yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.zip | |
Added black box modules for all the 7-series design elements (as listed in ug953)
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 21d1fb1ea..524fd1d4e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -69,6 +69,7 @@ struct SynthXilinxPass : public Pass { log("\n"); log(" begin:\n"); log(" read_verilog -lib +/xilinx/cells_sim.v\n"); + log(" read_verilog -lib +/xilinx/cells_xtra.v\n"); log(" read_verilog -lib +/xilinx/brams_bb.v\n"); log(" read_verilog -lib +/xilinx/drams_bb.v\n"); log(" hierarchy -check -top <top>\n"); @@ -165,6 +166,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "begin")) { Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); + Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v"); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); |