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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:24 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:24 -0700 |
commit | b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d (patch) | |
tree | bba5b86a004118e36f753fd9b76f62ef90b70970 /techlibs/xilinx/mux_map.v | |
parent | 691e145cda416787fe214b5533c6ac3c8047bb65 (diff) | |
download | yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.tar.gz yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.tar.bz2 yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.zip |
Revert "Remove wide mux inference"
This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
Diffstat (limited to 'techlibs/xilinx/mux_map.v')
-rw-r--r-- | techlibs/xilinx/mux_map.v | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v new file mode 100644 index 000000000..0fa8db736 --- /dev/null +++ b/techlibs/xilinx/mux_map.v @@ -0,0 +1,52 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * 2019 Eddie Hung <eddie@fpgeh.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module \$shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + generate + genvar i, j; + // TODO: Check if this opt still necessary + if (B_SIGNED) begin + if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + wire _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH < 3 || A_WIDTH <= 4) begin + wire _TECHMAP_FAIL_ = 1; + end + else begin + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); + end + endgenerate +endmodule |