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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 16:18:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 16:18:14 -0700 |
| commit | 44fc616fc701d698564d68a7facf210947b8bd9e (patch) | |
| tree | 398dd8ef506ad9b5e2f87538e6a4914119d19352 /techlibs/xilinx/mux_map.v | |
| parent | 4d6fac019a9a2ca3d2f0a05eb8d08c88e04faad0 (diff) | |
| download | yosys-44fc616fc701d698564d68a7facf210947b8bd9e.tar.gz yosys-44fc616fc701d698564d68a7facf210947b8bd9e.tar.bz2 yosys-44fc616fc701d698564d68a7facf210947b8bd9e.zip | |
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
Diffstat (limited to 'techlibs/xilinx/mux_map.v')
| -rw-r--r-- | techlibs/xilinx/mux_map.v | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v index 4c1bb7d05..89586d3c3 100644 --- a/techlibs/xilinx/mux_map.v +++ b/techlibs/xilinx/mux_map.v @@ -55,14 +55,13 @@ module \$shiftx (A, B, Y); if (B_SIGNED) begin if (B_WIDTH < 4 || A_WIDTH <= 4) wire _TECHMAP_FAIL_ = 1; - else - // Since negative indices are out of the range of A - // and hence return 'bx, drop the sign bit + else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 \$__XILINX_SHIFTX #( .A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), - .B_WIDTH($clog2(A_WIDTH*B_WIDTH)), + .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y) |