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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-02-06 10:10:40 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 3b2f95953c8b8343f2696c5f47bfb2864417a8b1 (patch) | |
| tree | bdbd5f370d53e9f5fd164c61c4cd9c35f2da27de /techlibs/xilinx/lut4_lutrams.txt | |
| parent | e4d811561cfb8e7acdbd70dd500600427e3a1756 (diff) | |
| download | yosys-3b2f95953c8b8343f2696c5f47bfb2864417a8b1.tar.gz yosys-3b2f95953c8b8343f2696c5f47bfb2864417a8b1.tar.bz2 yosys-3b2f95953c8b8343f2696c5f47bfb2864417a8b1.zip | |
xilinx: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/xilinx/lut4_lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lut4_lutrams.txt | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/techlibs/xilinx/lut4_lutrams.txt b/techlibs/xilinx/lut4_lutrams.txt deleted file mode 100644 index 2b344a9ee..000000000 --- a/techlibs/xilinx/lut4_lutrams.txt +++ /dev/null @@ -1,19 +0,0 @@ -bram $__XILINX_RAM16X1D - init 1 - abits 4 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - - -match $__XILINX_RAM16X1D - min bits 2 - min wports 1 - make_outreg -endmatch |