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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-23 17:42:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-23 17:42:40 +0100 |
| commit | 1d8161b432fd5bc7fc03c21033f90d2a80cf741f (patch) | |
| tree | 3d978b639e5acde60f19ae4a5cc9a32752f0aa1c /techlibs/xilinx/drams_map.v | |
| parent | 318be8651c62f924176ed30043a35a89fb468df0 (diff) | |
| download | yosys-1d8161b432fd5bc7fc03c21033f90d2a80cf741f.tar.gz yosys-1d8161b432fd5bc7fc03c21033f90d2a80cf741f.tar.bz2 yosys-1d8161b432fd5bc7fc03c21033f90d2a80cf741f.zip | |
Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/xilinx/drams_map.v')
0 files changed, 0 insertions, 0 deletions