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| author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
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| committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
| commit | 0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7 (patch) | |
| tree | 9ed03b8345847046143161c3a63b8fa599393da2 /techlibs/xilinx/drams.txt | |
| parent | 2454ad99bf49afe752d6fd1c1567f59ee9e26736 (diff) | |
| parent | 0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3 (diff) | |
| download | yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.gz yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.bz2 yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/xilinx/drams.txt')
| -rw-r--r-- | techlibs/xilinx/drams.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt index 91632bcee..2613c206c 100644 --- a/techlibs/xilinx/drams.txt +++ b/techlibs/xilinx/drams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM64X1D init 1 abits 6 @@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM64X1D min bits 5 min wports 1 |