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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-13 13:40:30 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-13 13:40:30 +0100 |
| commit | f0b2d8e467998876ad2cc14232d30ff7892982a3 (patch) | |
| tree | 66ef3713fd8b1b92a6585b1a9f3b225afd4fa2eb /techlibs/xilinx/cells_xtra.sh | |
| parent | 1cd04a68389671c91dddb56cc3d2f9032f9b44e3 (diff) | |
| parent | 9284cf92b8dcb510a2a9511965e587e42944c543 (diff) | |
| download | yosys-f0b2d8e467998876ad2cc14232d30ff7892982a3.tar.gz yosys-f0b2d8e467998876ad2cc14232d30ff7892982a3.tar.bz2 yosys-f0b2d8e467998876ad2cc14232d30ff7892982a3.zip | |
Merge pull request #868 from YosysHQ/clifford/fixmem
Various mem2reg-related improvements in handling of memories
Diffstat (limited to 'techlibs/xilinx/cells_xtra.sh')
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