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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:22 -0800 |
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| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:22 -0800 |
| commit | 73ddab6960a02aef0c5f9ccee8cee2e666778c06 (patch) | |
| tree | 3bdc3d5b0c18f279645138475a89b2dff2f94b38 /techlibs/xilinx/cells_xtra.sh | |
| parent | 8aab7fe7e64b1c213d924126e30994ab7b6d4625 (diff) | |
| download | yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.tar.gz yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.tar.bz2 yosys-73ddab6960a02aef0c5f9ccee8cee2e666778c06.zip | |
Add SRL16 and SRL32 sim models
Diffstat (limited to 'techlibs/xilinx/cells_xtra.sh')
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