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author | Clifford Wolf <clifford@clifford.at> | 2019-07-11 07:23:28 +0200 |
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committer | GitHub <noreply@github.com> | 2019-07-11 07:23:28 +0200 |
commit | fd3d5cefad89a396c9807bf3b8dc7349c1a765f1 (patch) | |
tree | 3949a915bb2a9d3a0c06f77460a2a97518f07563 /techlibs/xilinx/cells_sim.v | |
parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
parent | ea447220dab2a5a66adb3a78ca2789068f046f3a (diff) | |
download | yosys-fd3d5cefad89a396c9807bf3b8dc7349c1a765f1.tar.gz yosys-fd3d5cefad89a396c9807bf3b8dc7349c1a765f1.tar.bz2 yosys-fd3d5cefad89a396c9807bf3b8dc7349c1a765f1.zip |
Merge pull request #1179 from whitequark/attrmap-proc
attrmap: also consider process, switch and case attributes
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
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