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authorEddie Hung <eddie@fpgeh.com>2019-08-20 18:17:14 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-20 18:17:14 -0700
commitf1a206ba03c5b6fba2672754d09cc649a60beeb8 (patch)
tree378ddd9860014548bee29a57d5eb285fa75b244d /techlibs/xilinx/cells_sim.v
parent091bf4a18b2f4bf84fe62b61577c88d961468b3c (diff)
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Revert "Remove sequential extension"
This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
-rw-r--r--techlibs/xilinx/cells_sim.v24
1 files changed, 8 insertions, 16 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d879a56ee..1ab718ccc 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,8 +211,7 @@ endmodule
`endif
-module FDRE ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, R);
+module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -224,8 +223,7 @@ module FDRE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate
endmodule
-module FDSE ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, S);
+module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -237,8 +235,7 @@ module FDSE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate
endmodule
-module FDCE ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, CLR);
+module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -252,8 +249,7 @@ module FDCE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate
endmodule
-module FDPE ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, PRE);
+module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -267,29 +263,25 @@ module FDPE ((* abc_arrival=303 *) output reg Q,
endcase endgenerate
endmodule
-module FDRE_1 ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, R);
+module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
-module FDSE_1 ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, S);
+module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
-module FDCE_1 ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, CLR);
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
-module FDPE_1 ((* abc_arrival=303 *) output reg Q,
- input C, CE, D, PRE);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;