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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
| commit | c340fbfab23c582103402bbd812d9bca4510dc41 (patch) | |
| tree | 6aef6aa91610b8247b97ad9eb7fc0308bc294915 /techlibs/xilinx/cells_sim.v | |
| parent | 11ac37733d436d5c0217fa6da029d620ec3da1b3 (diff) | |
| download | yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.gz yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.bz2 yosys-c340fbfab23c582103402bbd812d9bca4510dc41.zip | |
Force $inout.out ports to begin with '$' to indicate internal
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions