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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:23:31 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 16:23:31 +0100 |
| commit | 8c3de1d4bd8a08756dee569430c03229e9e89a95 (patch) | |
| tree | 5b899b27cf3f25d7708960004b7d7657fedcd253 /techlibs/xilinx/cells_sim.v | |
| parent | a82c701668d8197c01e54cb68bc45f2278f3172f (diff) | |
| parent | 9e6632c40ac24d8839bb76ca2f9674edfdc750f9 (diff) | |
| download | yosys-8c3de1d4bd8a08756dee569430c03229e9e89a95.tar.gz yosys-8c3de1d4bd8a08756dee569430c03229e9e89a95.tar.bz2 yosys-8c3de1d4bd8a08756dee569430c03229e9e89a95.zip | |
Merge remote-tracking branch 'origin/master' into iopad_default
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 804c2d70f..3bcbfc9aa 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2099,7 +2099,7 @@ always @* begin 2'b00: XMUX <= 0; 2'b01: XMUX <= M; 2'b10: XMUX <= P; - 2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT}; + 2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT}; default: XMUX <= 48'hxxxxxxxxxxxx; endcase end @@ -2117,8 +2117,8 @@ end // The post-adder. wire signed [48:0] X_EXT; wire signed [48:0] Z_EXT; -assign X_EXT = XMUX; -assign Z_EXT = ZMUX; +assign X_EXT = {1'b0, XMUX}; +assign Z_EXT = {1'b0, ZMUX}; assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); // Cascade outputs. |