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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 21:30:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 21:30:16 -0700 |
| commit | 8182cb9d91555d5be52abbfeeb5d22af05342d8a (patch) | |
| tree | 0f464109754ad70093d12939e1b0b122889c4813 /techlibs/xilinx/cells_sim.v | |
| parent | 4d123b7638b7036da70de169d16d2ae21b89b8e2 (diff) | |
| download | yosys-8182cb9d91555d5be52abbfeeb5d22af05342d8a.tar.gz yosys-8182cb9d91555d5be52abbfeeb5d22af05342d8a.tar.bz2 yosys-8182cb9d91555d5be52abbfeeb5d22af05342d8a.zip | |
Fix omode which inserts an output if none exists (otherwise abc9 breaks)
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions