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| author | whitequark <whitequark@whitequark.org> | 2019-07-09 18:30:24 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-07-09 18:35:49 +0000 |
| commit | 6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5 (patch) | |
| tree | 93563c725c5c63fcf1298b332ed8df8c95057288 /techlibs/xilinx/cells_sim.v | |
| parent | e95ce1f7af269447943cf1798c03b02a0c5aa1a2 (diff) | |
| download | yosys-6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5.tar.gz yosys-6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5.tar.bz2 yosys-6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5.zip | |
write_verilog: write RTLIL::Sa aka - as Verilog ?.
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions