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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:52:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:52:27 -0700 |
| commit | 54284aaa986800b8623d401fd93cf92d25d13713 (patch) | |
| tree | 3d2d52add727a3388533e89ec2b178ee4adf17d1 /techlibs/xilinx/cells_sim.v | |
| parent | 96f00e9147967b587ee3b0118b944464b06da0b6 (diff) | |
| download | yosys-54284aaa986800b8623d401fd93cf92d25d13713.tar.gz yosys-54284aaa986800b8623d401fd93cf92d25d13713.tar.bz2 yosys-54284aaa986800b8623d401fd93cf92d25d13713.zip | |
Remove delays from abc_map.v
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions