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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:31:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:31:19 -0700 |
| commit | 36a219063ad7b4e70581bf83a00365db764737bf (patch) | |
| tree | 13f467cdcabe60bf91d2adf2e0269bd72a0cda14 /techlibs/xilinx/cells_sim.v | |
| parent | fb09c6219b057100d2e43028ec710888c20924fd (diff) | |
| download | yosys-36a219063ad7b4e70581bf83a00365db764737bf.tar.gz yosys-36a219063ad7b4e70581bf83a00365db764737bf.tar.bz2 yosys-36a219063ad7b4e70581bf83a00365db764737bf.zip | |
Modify LUT area cost to be same as old abc
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
0 files changed, 0 insertions, 0 deletions