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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 09:49:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 09:49:41 -0700 |
| commit | 146451a767bc0ba77da86bdb8ebec5d3387b49ca (patch) | |
| tree | 4477f092c352de034fef1a315a542778185d90ce /techlibs/xilinx/cells_sim.v | |
| parent | b33ecd2a746b734fda33d8535afecf76bd35f59c (diff) | |
| parent | a97d30d2f88d2f7a41abf8b913bbc017b60d8c7d (diff) | |
| download | yosys-146451a767bc0ba77da86bdb8ebec5d3387b49ca.tar.gz yosys-146451a767bc0ba77da86bdb8ebec5d3387b49ca.tar.bz2 yosys-146451a767bc0ba77da86bdb8ebec5d3387b49ca.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3937d3536..05e46b4e7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -226,7 +226,7 @@ module FDRE (output reg Q, input C, CE, D, R); endmodule module FDSE (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; @@ -252,7 +252,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); endmodule module FDPE (output reg Q, input C, CE, D, PRE); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; |